Hardware setup:

Connect the tileboard to the tileboard tester (TBT) through the QTH/QSH port via the adapter and power on the TBT (~10 V)

1. Place the tileboard with the screw mounts such that the surface with SiPMs, LEDs and tiles is facing downwards, and the face with the HGCROC, GBTSCA etc mounted points upwards
2. Rigol dual power supply (digital, controlled with RPi - see below) and an analog tileboard power supply are used
   • Connect the yellow cable of the adapter to the SiPM bias, the green cable to the LED bias and the red cable to the tileboard supply - they are all banana jacks of very short length (cables are all labeled)
   • Connect the black cable (board GND) to the negative terminals of one of the power supplies, short all the three negative terminals to their respective GNDs and short the 3 GNDs together
   • Tileboard bias should be ~10 V (ideally 10.5 V or 11 V and not exceeding 12 V (verify this max))

1. Place the tileboard such that the surface with SiPMs, LEDs and tiles is facing upwards, and the face with the HGCROC, GBTSCA etc mounted points downwards
2. The external tileboard bias will not be used since the power to the tileboard is directly provided by the TBT through the ribbon cable
3. The external LED bias will not be used either, since the value can be entered with a DAC in the script https://github.com/snabili/HGCal_QCTests/blob/main/sipm_mezz_v2.py using python ./sipm_mezz_v2.py --setLED="digital_value" --status, and the status argument outputs the voltage and current for the LED and SiPMs

Voltage control with USB from Raspberry Pi:

Software setup:

Internal IP Address of Gantry desktop - 10.42.0.200

Two terminal windows to be opened by logging (ssh) into the TBT [for daq-server i.e. the fast controls server and i2c-server i.e. the slow control server] and two windows on the remote machine, which is the gantry desktop [for the daq-client and the actual script to be run]

Scripts are in the $hostarea/hexactrl-sw/hexactrl-script

PLL_LCK=1

VCC_GBTSCA ~ 1.5 V

VPA (HGCROC supply voltage) ~2.5 V

* Other diagnostic parameters -

- Run the slow control script and measure CLK and data signals (SCL and SDA) at R182 and R181

This will produce several (10000 is the current setting) events for each channel and plot the average and stddev (noise) for each channel

Current issues:

Very large noise levels obtained for the second half of the board (half 1) due to bimodal pedestals which in turn arise due to corruption in a significant proportion of the events (from 10% upto 70% for some runs)

This has been resolved to some extent by not including the RPi in the tileboard tester ssh path

Pedestal alignment:

1. Channelwise inverting shaper voltage (ref_dac_inv)
2. Global inverting shaper voltage (10 bit Inv_vref)
3. Global non inverting shaper voltage (10 bit Noinv_vref)
4. Channelwise leakage current at conveyor stage (6 bit DACb) - This is the main parameter responsible for the flattening

At the moment steps 2 and 4 are working, step 1 is producing a key error in ref_dac_inv, and the fit in step 3 is failing

This gives a pedestal value close to 0, and this gives problems with producing a single photon spectrum (sps) via external injection [Not actually the purpose of pedestal alignment]

New version (ROC v3)

Apparently ref_dac_inv is now trim_inv, which is tuned using a pedestal scan script

1. Pedestal scan (setting targets individually for either half of the board)
2. Tuning in global inverting shaper voltage (10 bit Inv_vref)
3. Pedestal scan again (to refine the results)

SPS (Single Photon Spectrum) with Phase scan via external injection

Phase scan is only done to find the phase (slice in time) where the integrated pulse amplitude is maximum for best sps results - each phase is associated with its own separate .root file